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[Com Port] uartok

Description: 采用verilog编写的串口通信程序，采用了状态机设计！程序简单，消耗资源少-Serial communication written by verilog hdl. It is designed with FSM. The program is simple,and consume resource is few.
Platform: | Size: 431104 | Author: 陈旭 | Hits:

[Com Port] uart_verilog_v1

Description: uart d的verilog 程序，可以实现普通串口功能-UART d Verilog procedures can be achieved ordinary serial port function
Platform: | Size: 5120 | Author: 梁启 | Hits:

[Communication] uart_verilog

Description: verilog & vhdl以及外国公司的应用说明。-Verilog
Platform: | Size: 148480 | Author: 丁路杰 | Hits:

[Other Embeded program] UART_BooQuai

Description: FPGA上实现UART串口原程序，在ISE6编写的-FPGA serial UART to achieve the original procedure, the preparation of the ISE6
Platform: | Size: 11264 | Author: 樊 | Hits:

[Other] uartvhrilog

Description: This Verilog HDL description implements a UART.
Platform: | Size: 3072 | Author: chenhe | Hits:

[Software Engineering] m16550a_verilog_rtl

Description: mentor UART IP verilog源码 以通过验证.-mentor UART IP verilog source to the test.
Platform: | Size: 25600 | Author: cray | Hits:

[VHDL-FPGA-Verilog] Uart_TR

Description: Verilog编写的简单异步串口 完全原创，站长请查看内容-Verilog prepared by the simple asynchronous serial completely original, the station can be accessed content
Platform: | Size: 289792 | Author: 李馨帆 | Hits:

[Other] PCI_Bridge_Guest_UART

Description: 这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序，用verilog实现，ise7.1，不知道这里可不可以上传硬件的程序~-pci-wishbone nuclear and nuclear Serial 16,450 in the TP xilinx They achieved a serial program, verilog realization ise7.1. Can here do not know the procedures upload hardware ~
Platform: | Size: 8427520 | Author: heartbeat | Hits:

[VHDL-FPGA-Verilog] uart_core_vhdlORverilog

Description: 串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\uart 源码 (Verilog)\uart 源码 (VHDL)\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \ uart source (Verilog) \ uart source (VHDL) \ uart16550.tar
Platform: | Size: 294912 | Author: efly | Hits:

[VHDL-FPGA-Verilog] uart_verilog

Description: uart串行口,用Verilog编写的.供大家参考-uart serial port, using Verilog prepared. For your reference
Platform: | Size: 10240 | Author: lfy | Hits:

[VHDL-FPGA-Verilog] VHDL_to_UART

Description: 用VHDL编写的串口通讯程序，包括几个不同的程序例子，也可以用verilog进行改写。
Platform: | Size: 3072 | Author: 汪毅 | Hits:

[Com Port] UART

Description: UART_verilog,自己设计的异步串行收发。包括测试文件。-UART_verilog, designed to send and receive asynchronous serial. Including the test file.
Platform: | Size: 6144 | Author: 甲壳虫 | Hits:

[VHDL-FPGA-Verilog] uartverlog

Description: 占用资源少的verilog HDL uart接口；采用固定波特率115200，可以修改程序中的分频来修改波特率，模式为1个启始位，8位数据位，1个停止位；带1字节缓存；当缓存空时输出空信号-Occupy fewer resources verilog HDL uart interface adopted a fixed baud rate of 115200, can modify the procedure to modify the baud rate frequency, the model of a start bit, 8 data bits, 1 stop bit with one word section of the cache when the cache empty space-time output signal
Platform: | Size: 2048 | Author: 张诚 | Hits:

[VHDL-FPGA-Verilog] tx

Description: 自己编写的串口UART发送的Verilog模块。与FIFO连接，可以实现自动连续发送。-I have written serial UART to send the Verilog module. Connect with the FIFO, you can realize automatic continuous send.
Platform: | Size: 7168 | Author: YongZhiLi | Hits:

[VHDL-FPGA-Verilog] rxd

Description: 自己编写的串口UART的接收Verilog模块，支持中断和查询方式接收，对信号的畸变适应能力强。-I have written serial UART reception Verilog modules, support and inquiries receive interrupt signal distortion adaptable.
Platform: | Size: 2048 | Author: YongZhiLi | Hits:

[VHDL-FPGA-Verilog] uartsourcecode

Description: uart的FPGA模块，基于VHDL、verilog语言-the FPGA UART modules, based on VHDL, verilog language
Platform: | Size: 293888 | Author: 王辉 | Hits:

[Com Port] uart2iic

Description: UART转I2C的Verilog HDL代码，由北京邮电大学《VerilogHDL设计与EDA技术基础》教师编写-UART to I2C of the Verilog HDL code, by the Beijing University of Posts and Telecommunications VerilogHDL design and EDA technology infrastructure Teacher preparation
Platform: | Size: 3072 | Author: emulous | Hits:

[assembly language] lcd_module

Description: verilog code which receive from uart RX and then output to lcd text display.
Platform: | Size: 2048 | Author: 蔡俊仪 | Hits:

[VHDL-FPGA-Verilog] uart_51

Description: 符合8051协议规范的UART的Verilog源代码.该压缩包是一个modelsim的工程.-8051 agreement in line with the norms of the Verilog source code UART. The Compression Pack is a ModelSim project.
Platform: | Size: 41984 | Author: 王亮 | Hits:

[Com Port] rec

Description: uart串口通信程序 用VERILOG HDL　编写　可以有效应用于FPGA上-UART serial communication program with VERILOG HDL can be effectively used in the preparation of the FPGA
Platform: | Size: 1024 | Author: 德刚 | Hits:
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